1. Field of the Invention
Embodiments of the invention relate generally to the field of memory devices and more particularly, to a serial peripheral interface (SPI) to NAND memory devices.
2. Description of the Related Art
A serial peripheral interface (SPI) is a communication interface that provides a relatively simple connection between two devices. The SPI includes a 4-wire serial bus that enables a master device to communicate with one or more slave devices. Data is simultaneously transmitted and received via the SPI, making it a full-duplexed protocol. The protocol provides for low/medium bandwidth (1 megabaud) network connection amongst processors and other devices.
The SPI generally has four wires that include two control lines and two data lines. The control lines include a serial clock (SCLK) line and a chip select (CS) line. The SCLK line is driven with a digital clock signal to regulate the flow of bits between devices. The CS is driven with a signal that enables or disables the slave device that is being controlled by the master device. The data lines include a Master Output/Slave Input (MOSI) line and a Master Input/Slave Output (MISO) line. The MOSI line is used to transfer data from an output of the master device to an input of the slave device. The MISO line is used to transfer data from an output of the slave device to an input of the master device.
The SPI's simple configuration of control and data lines enables the SPI to have a relatively high board density at a low cost. In other words, the four control lines are simple to route between components and may not take up a significant amount of surface area on a printed circuit board (PCB). Accordingly, the SPI interface may be beneficial for use in applications that desire compact and simple layouts, such as computers.
Computer systems and other electrical systems generally include one or more memory devices. For example, computers often employ NOR flash memory and NAND flash memory. NOR and NAND flash each have certain advantages over the other. For example, NOR flash memory typically has slower write and erase speeds than NAND flash. Further, NAND flash memory typically has more endurance than NOR flash memory. However, NOR flash memory typically enables random access to data stored within the memory devices, whereas, NAND flash memory generally requires accessing and writing data in larger groups. For example, NAND flash memory typically includes a plurality of blocks that each includes a plurality of pages, wherein each page includes a large number of bytes of data. In operation, data is erased one block at a time, and written one page at a time.
Generally, communication between a device, such as a processor and a NAND memory device is accomplished with a parallel interfaces. In other words, a plurality of connections is made between the devices and the NAND memory device to enable a simultaneous (parallel) transfer, as opposed to a serial transfer, of data between the device and the NAND memory. Unfortunately, the additional numbers of connections may increase the complexity of the interfaces, increase the amount of surface area used on a printed circuit board, and increase the noise (crosstalk) between the lines.
Embodiments of the present invention may be directed to one or more of the problems set forth above.